Recent changes in technology scaling have made power dissipation today's major performance limiter. As a result, designers struggle to meet performance requirements under stringent power budgets. At the same time, the traditional solution to power efficiency, application specific designs, has become prohibitively expensive due to increasing nonrecurring engineering (NRE) costs. Most concerning are the development costs for design, validation, and software for new systems.
One direction that industry has attempted, with the goal of mitigating the rising costs of per-application designs, is to add a layer of programmability that specifies how the hardware operates. An example of this approach includes baseband processors for software-defined-radio (SDR) wireless devices. Similarly, a study, Stanford Smart Memories (SSM), showed that it is possible to build a reconfigurable chip multiprocessor memory system that can be customized for specific application needs. These programmable, or reconfigurable, hardware solutions enable per-application customization and amortization of NRE costs—to a limited extent. But reconfigurability introduces overheads at the circuit level, and customization is limited to those resources that were decided upon, and verified, upfront.